A transceiver includes a transmitter and a receiver, thereby allowing the transceiver to both transmit and receive communication signals. Conventionally, the transmitter contains a power amplifier (PA) that provides the last stage of amplification of the signal to be transmitted.
In most conventional designs, the power amplifier is implemented as a component that is physically separate from other parts of the transmitter and/or transceiver. Also, power amplifiers made from gallium arsenide (GaAs) or Silicon bipolar junction transistors (SiBJT) are typically used because they have an inherently higher breakdown voltage than transistors made in a CMOS circuit, whether the transistors are n-channel or p-channel transistors. While such designs allow for a power amplifier that has the desired amplification characteristics, they do so at the expense of cost. Not only is a GaAs, SiBJT or other non-CMOS power amplifier costlier than a transistor in a CMOS integrated circuit, but the non-CMOS power amplifier cannot be formed on the same integrated circuit chip as the components of the transmitter and/or transceiver. Both of these factors add to the overall cost of the resulting transceiver.
Therefore, it would be beneficial to have a transceiver in which most of the transmitter and receiver circuits are on a single chip, including the power amplifier. For example, an article entitled “A Single Chip CMOS Direct-Conversion Transceiver for 900 MHz Spread Spectrum Digital Cordless Phones” by T. Cho et al. that was presented at the 1999 IEEE International Solid State Circuits Conference, describes a CMOS transceiver chip that includes an integrated power amplifier. An improved CMOS power amplifier is also described in U.S. Pat. No. 6,504,433, entitled “CMOS TRANSCEIVER HAVING AN INTEGRATED POWER AMPLIFIER”, filed on Sep. 15, 2000, and assigned to Atheros Communications, Inc., which recognizes the advantage of integrating the power amplifier.
Nevertheless, a major disadvantage of CMOS power amplifiers is that they exhibit a wide range of power level variation due to their sensitivity to thermal and process variations. High efficiency and constant power levels in CMOS power amplifiers is impeded by the technologies low breakdown voltage, low current drive, and lossy substrate.
Furthermore, conventional transmitter designs operate so that the output power is transmitted based upon a function of many different variables. For example, in a Code Division Multiple Access (CDMA) environment, the power output of a mobile transmitter will typically be based upon the distance between the mobile transmitter and the base station currently in use. In such an environment, the output power will generally increase if the mobile transmitter travels closer to the base station. In operation, the gain of a variable gain amplifier that is part of the transmitter, at either the intermediate frequency (IF) or radio frequency (RF) stage, will be changed to thereby lower the transmit output power. In this situation, while the output power may become too large for a period of time, that is acceptable within the overall system requirements.
However, in other environments, it is required (by for instance the Federal Communication Commission (FCC)) that the output power must not exceed a pre-specified level at any time. In such an environment, the above-described design cannot be used. Specifically, in order to take into account instances in which power will exceed the pre-specified maximum, the average output power must be much lower than that maximum, which degrades system performance to an unacceptable level.
Accordingly, a transmitter containing a variable gain amplifier and a power amplifier integrated with a CMOS transceiver chip that overcomes the above disadvantage would be desirable.